This application claims priority to Korean Patent Application No. 2003-35608, filed on Jun. 3, 2003, and Korean Patent Application No. 2003-64202, filed on Sep. 16, 2003, in the Korean Intellectual Property Office, the disclosures of which are incorporated herein by reference in their entirety.
1. Technical Field
The present disclosure relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device with a trench gate type transistor and a method of manufacturing the same.
2. Discussion of Related Art
As the integration density of semiconductor devices, such as DRAMs, has increased, the size of memory cells has been scaled down. A reduction in the memory cell size requires a reduction in the size of cell transistors. Thus, many new methods have been developed to secure a predetermined cell capacitance in a memory cell having a reduced size cell transistor. Cell transistors are required to maintain excellent characteristics despite their reduction in size. Thus, various methods of controlling the concentration of impurity ions in diffusion layers have been proposed. However, as the channel length is reduced, it is difficult to control the depth of the diffusion layers during a semiconductor device manufacturing process that includes various thermal processes. Also, since the effective channel length is decreased and the threshold voltage is reduced, a short channel effect may occur, which seriously degrades the operation of the cell transistors.
A trench gate type transistor, in which a trench is formed in a surface of a substrate and a gate electrode is formed in the trench, has been developed. The trench gate type transistor can improve short channel effects in the transistor because the gate electrode is formed in the trench to extend a source-drain distance and increase the effective channel length.
In conventional methods of manufacturing a trench gate type transistor, an isolation region is formed that defines an active region in a semiconductor substrate, and then a trench is formed in the active region of the semiconductor substrate to form a gate electrode (for example, refer to U.S. Pat. No. 6,476,444 and U.S. Pat. No. 6,498,062).
However, if the trench, which is required for forming the gate electrode, is formed after the isolation region is formed as described above, an undesired short channel may be formed between the isolation region and the gate electrode when a distance between the isolation region and the gate electrode is short.
The formation of the undesired short channel will be described in more detail with reference to FIG. 1. FIG. 1 is a sectional view of a conventional semiconductor device. Referring to FIG. 1, an isolation region 12 is formed by a shallow trench isolation (STI) process in a semiconductor substrate 10. A sidewall 12a of the isolation region 12, which contacts an active region 14, is sloped due to a taper etch process. When a gate trench 16 is formed to form a gate electrode 20, a sidewall 16a of the gate trench 16 is also sloped due to a taper etch process. As a result, when a distance between the isolation region 12 and the gate electrode 20 is sufficiently small, as illustrated in FIG. 1, after a cell transistor is completed, a narrow silicon region 18 caused by the sloped sidewalls 12a and 16a may remain between the isolation region 12 and the gate electrode 20 in the semiconductor substrate 10. The silicon region 18 leads to an undesired channel between the isolation region 12 and the gate electrode 20. As a result, the cell transistor cannot ensure a sufficient threshold voltage.
A method of controlling an angle of inclination of a trench profile during an etch process for forming a gate trench or a method of using a wet etch process may be considered. However, these methods cannot completely remove a remaining silicon region between an isolation region and a gate electrode. Consequently, an undesired short channel may remain, thus adversely affecting the reliability of the resultant transistor.